Method of forming storage node of capacitor in semiconductor memory, and structure therefor

ABSTRACT

In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

This application is a Divisional of U.S. patent Ser. No. 10/871,322,filed on Jun. 18, 2004, now pending, which claims priority from KoreanPatent Application No. 2003-39786, filed on Jun. 19, 2003, both of whichare hereby incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices, and moreparticularly, to a method of forming a storage node of capacitor in asemiconductor memory such as a DRAM (Dynamic Random Access Memory) and astructure thereof.

2. Description of the Related Art

A memory cell of DRAM is generally constructed of one access transistorand one storage capacitor. The capacitor is largely classified as alaminated type or a trench type depending on its formed position on asemiconductor substrate.

Semiconductor manufacturers for manufacturing a semiconductor memorythat employs the laminated-type capacitor have continuously researchedproducing capacitors with a higher capacitance in a limited area inconformity with various requirements of semiconductor users. The needfor this continuous research is derived from the high integration ofmemory cells that produces a tightened critical dimension which resultsin low capacitance of the memory cells. However, in order to guarantee arefresh operating period within a range of regulated value, thecapacitance must instead be increased.

Capacitors are generally composed of a storage node as a lower electrodenode and a plate node as an upper electrode. High integration causes thebottom critical dimension (CD) of the storage node to be too small whichcauses a leaning phenomenon resulting in the collapse of the storagenode.

To prevent the leaning phenomenon, two methods have widely been used inthis field. First is the method of increasing the bottom CD of straighttype storage node. Second is the a method of lowering the height ofstorage node. However, the straight type method is undesirable becauseit is difficult to increase the bottom CD after a design rule was firstdecided, and the latter method is undesirable because it is unlikely toobtain the desired capacitance.

The former method was recently improved to provide a larger bottom CDand reduce the occurrence rate of the leaning phenomenon within alimited area. In this improved method, and in forming the storage nodeof the capacitor, an active region, a gate, a bit line contact, astorage node contact or buried contact, and bit line patterns are formedin a diagonal direction slightly slanted as compared with the existingstraight structure, and thereon, the capacitor storage node is formed.This improved method significantly increases the bottom CD of thestorage node as compared with the storage node of the existing straighttype, and this is known in this field as a diagonal structure. However,this diagonal structure has severely complicated manufacturing processesin forming the storage node.

To avoid the complicated manufacturing processes of the diagonalstructure, a new method for forming a storage node of square type wasrecently developed which shared advantages of the straight structure andthe diagonal structure. In this method for the square type, an activeregion, a gate, a bit line and a capacitor storage node contact etc. areformed by the existing straight structure. Then, entirely thereon, abuffer layer is formed, and a contact is formed in the buffer layer, tothus connect the capacitor storage node of square type with a capacitorstorage node contact of the straight structure. This new method has beenregarded as increasing the storage node of the square type so that thebottom CD of the capacitor storage node is largely increased to abouttwice that of the storage node of the straight type based on thestraight structure.

The method of manufacturing the storage node of square type in the priorart will be described referring to FIGS. 1 through 6, as follows, onlyto provide a thorough understanding of the present invention to bedescribed later.

FIG. 1 is a plan view illustrating a disposed relationship for storagenodes of capacitor based on a square type in a semiconductor memoryaccording to an example of the prior art. FIGS. 2 to 6 are sectionalviews showing sequential processes in manufacturing the storage nodereferred to FIG. 1.

Referring first to FIG. 1, vertically on the drawing, six word linepatterns 13 as gates of a plurality of access transistors are formed,and horizontally on the drawing, four bit line patterns 16 connected todrains of the access transistors are formed. Storage nodes 23 of squaretype of the capacitors form an oblong structure in a diagonal directionto the bit line patterns 16 and the word line patterns 13. Herewith,each contact 17 of the storage node of capacitor and its lower structureare formed by a straight structure as the afore-mentioned. A referencenumber 14 indicates a bit line contact for connecting a bit line with adrain, and 14 a designates a bit line pad. FIGS. 2 to 6 are sectionalviews taken along A-A′ and B-B′ cutting lines shown in FIG. 1.

On the left drawings of FIGS. 2 through 6, cross-sectional views takenalong A-A′ cutting line direction of FIG. 1, namely, the direction of aword line connected to a gate of access transistor, are illustrated perprocess. On the right drawings of FIGS. 2 to 6, cross-sectional viewstaken along B-B′ cutting line direction of FIG. 1, namely, the directionof a bit line connected to a drain of the access transistor, areillustrated per process.

FIG. 2 illustrates a structure before forming a storage node ofcapacitor having a square type in a DRAM based on a capacitor overbitline (COB) structure. A device separate layer 3 is formed on adetermined region of a semiconductor substrate 11 to define a pluralityof active regions. A gate oxide layer 5 is formed on the active regions.Thereon, a plurality of parallel word line patterns 13 traversing theactive regions are formed. The word line pattern 13 contains a word line7 b and a capping layer pattern 7 c laminated sequentially. An impurityion is implanted into the active regions by using the word line pattern13 and the device separate layer 3 as an ion implantation mask, to formimpurity regions 4 s, 4 d. The active impurity regions 4 d between onepair of word line patterns 13 traversing the respective active regionsare pertinent to a common drain region of a DRAM cell transistor.Further, the impurity region 4 s formed on both sides of each commondrain region 4 d is pertinent to a source region of the DRAM celltransistor. A word line spacer 7 a is formed on a sidewall of the gateoxide layer 5 and the word line patterns 13. A first interlayerinsulation layer 13 a is formed on an entire face of the semiconductorsubstrate containing the word line spacer 7 a. The first interlayerinsulation layer 13 a is etched by using an etch mask pattern, to formthe bit line pad 14 a connected with the common drain region 4 d and acapacitor storage node pad 12 connected with the source region 4 s.Then, a second interlayer insulation layer 16 a is formed on an entireface of the semiconductor substrate containing the bit line pad 14 a andthe capacitor storage node pad 12. The second interlayer insulationlayer 16 a is patterned to form the bit line contact 14 referred toFIG. 1. Then, the bitline contact 14 is connected with the plurality ofbit line patterns 16 having a sidewall spacer 15. The bit line patterns16 are formed, involving a bit line 16 b and a bit line capping layerpattern 16 c each laminated sequentially and traversing the word linepatterns 13. Each bit line 16 b is electrically connected to the bitline pad 14 a through the bit line contact 14. A third interlayerinsulation layer 15 a is formed on an entire face of the semiconductorsubstrate containing the bit line spacer 15. The third interlayerinsulation layer 15 a and the second interlayer insulation layer 16 aare continuously patterned to form a capacitor storage node contact 17.

The lower structure of semiconductor substrate composed of the activeregion 4 s, 4 d, the bitline contact 14, the capacitor storage node pad12, the bitline pattern 16, the word line pattern 13 and the capacitorstorage node contact 17 etc., is formed by the straight structure.

Referring to FIG. 3, a buffer layer 18 is formed on the semiconductorsubstrate 11 having the capacitor storage node contact 17. An aperturefor connecting the storage node of square type with the capacitorstorage node contact 17 is formed through a photolithography and etchingprocess. Metallic material such as tungsten etc. is deposited in theaperture and then a flattening is performed to form a pad contact 19.

Referring to FIG. 4, film material such as silicon nitride layer etc. isdeposited to form an etching stop layer 20 on the semiconductorsubstrate having the pad contact 19. Thereon, a mold oxide layer 21 fora formation of the storage node of capacitor is formed by a thickthickness.

In FIG. 5, an etching mask pattern is formed in the mold oxide layer 21,and an aperture part 22 is formed to expose an upper part of the padcontact 19 connected with the storage node of the capacitor, through anetching process.

In FIG. 6, a chemical vapor deposition (CVD) process is performed on anentire face of the semiconductor substrate having the aperture part 22,to form a conductive layer 23 of polysilicon etc. The conductive layerremained on an upper part of the mold oxide layer is removed through aprocess such as a flattening etc., to form the capacitor storage node ofsquare type. The capacitor storage node 23 a through 23 e of square typeprovides a sectional face of the storage node of the capacitor based onthe square type referred to FIG. 1.

In the prior art described above, in order to form a capacitor storagenode of square type on a semiconductor substrate based on a conventionalstraight lower structure, a buffer layer is adapted. Thus, there is aproblem of an additional step of forming a pad contact on the bufferlayer, the pad contact being for connecting the storage node of squaretype with a storage node contact of straight structure.

SUMMARY OF THE INVENTION

In one embodiment, an etch stop layer and a mold layer is sequentiallyformed on a semiconductor substrate having an interlayer insulationlayer. The interlayer insulation layer includes a conductive regionformed therein. The mold layer is partially etched to expose a topsurface of the etching stop layer. The exposed etching stop layer and anupper portion of the interlayer insulating layer are removed to form afirst aperture part that exposes a portion of the conductive region. Theconductive region exposed in the first aperture part is etched to form asecond aperture part. A conductive layer for the capacitor storage nodeis deposited on the semiconductor substrate having the first and secondaperture parts. The conductive layer provided on the mold layer isplanarized to form separated capacitor storage nodes.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of exemplary embodiments of the presentinvention will become readily apparent from the description of theexemplary embodiment that follows, Referring to the attached drawings inwhich:

FIG. 1 is a plan view illustrating a disposed relationship of storagenodes of capacitors based on a square type in a semiconductor memoryaccording to the prior art.

FIGS. 2 through 6 are cross-sectional views of sequential processes formanufacturing the storage node referred to FIG. 1.

FIG. 7 is a plan view illustrating a disposed relationship of storagenodes of capacitors based on a square type in a semiconductor memoryaccording to an exemplary embodiment of the present invention.

FIGS. 8 through 13 are cross-sectional views of sequential processes fora manufacturing of the storage node referred to FIG. 7.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

It will be understood by those skilled in the art that the presentinvention can be embodied by numerous different types and is not limitedto the following described embodiments. The following variousembodiments are exemplary in nature.

FIG. 7 is a plan view showing a capacitor storage nodes of a square typein a semiconductor memory according to an exemplary embodiment of thepresent invention. FIGS. 8 through 13 are cross-sectional views ofsequential processes for manufacturing the storage node referred to inFIG. 7.

Referring to FIG. 7, vertically on the drawing, six word line patterns113 as gates of a plurality of access transistors are formed, andhorizontally on the drawing, four bit line patterns 116 connected todrains of the access transistors are formed. Storage nodes 123 of thecapacitors based on a square type form an oblong structure in a diagonaldirection to the bit lines 116 and the word lines 113. Herewith, astorage node contact 117 of each capacitor storage node, an interlayerinsulation layer and its below structure are formed by a straightstructure as the afore-mentioned. The capacitor storage node 123 is incontact with an inner face of an aperture part 125 that is formed at aportion of the storage node contact 117 based on the straight structure,to be thus electrically connected to the storage node contact 117. Areference number 114 indicates a bit line contact for connecting a bitline with a drain, and 114 a designates a bit line pad. FIGS. 8 to 13are cross-sectional views taken along C-C′ and D-D′ cutting linesreferred to FIG. 7.

On the left drawings of FIGS. 8 through 13, cross-sectional views takenalong line C-C′ of FIG. 7, namely, a direction of a word line connectedto a gate of access transistor, are illustrated per process. On theright drawings of FIGS. 8 to 13, cross-sectional views taken along lineD-D′ of FIG. 7, namely, a direction of a bit line connected to a drainof the access transistor, are illustrated per process.

FIG. 8 illustrates a structure before forming a storage node ofcapacitor having a square type in a DRAM based on a capacitor overbitline (COB) structure. A device separate layer 103 is formed on adetermined region of a semiconductor substrate 111 to define a pluralityof active regions. A gate oxide layer 105 is formed on the activeregions. Thereon, a conductive layer and a word line capping layer areformed sequentially. The conductive layer is formed of polysilicon layeror metallic polycide layer. The word line capping layer can be desirablyformed of silicon nitride layer. The word line capping layer and theconductive layer are continuously patterned to form a plurality ofparallel word line patterns 113 traversing the active regions. The wordline pattern 113 contains a word line 107 b and a capping layer pattern107 c laminated sequentially. An impurity ion is implanted into theactive regions by using the word line patterns 113 and the deviceseparate layer 103 as an ion implantation mask, to form impurity regions104 s, 104 d. The active impurity regions 104 d between one pair of wordline patterns 113 traversing the respective active regions are pertinentto a common drain region of a DRAM cell transistor. Further, theimpurity regions 104 s formed on both sides of the common drain region104 d are pertinent to a source region of the DRAM cell transistor. Aword line spacer 107 a is formed on a sidewall of the gate oxide layer105 and the word line patterns 113 through a general method. The wordline spacer 107 a can be desirably formed of material layer same as theword line capping layer pattern 107 c. A first interlayer insulationlayer 113 a is formed on an entire face of the semiconductor substratecontaining the word line spacer 107 a. The first interlayer insulationlayer 113 a is etched by using an etch mask pattern, to form the bitline pad 114 a connected with the common drain region 104 d and acapacitor storage node pad 112 connected with the source region 104 s.Then, a second interlayer insulation layer 116 a is formed on an entireface of the semiconductor substrate containing the bit line pad 114 aand the capacitor storage node pad 112. The second interlayer insulationlayer 116 a is patterned to form the bit line contact 114 referred toFIG. 7. Then, the plurality of bit line patterns 116 having a sidewallspacer 115 are formed being connected with the bitline contact 114. Thebit line patterns 116 are formed traversing the word line patterns 113.The bit line pattern 116 involves a bit line 116 b and a bit linecapping layer pattern 116 c laminated sequentially. The bitline 116 b isformed of a conductive layer such as a tungsten layer or tungstenpolycide layer, and the bitline capping layer pattern 116 c is formed ofsilicon nitride layer. The bitline spacer 115 is formed at a sidewall ofthe bitline 116 b. The bitline spacer 115 is formed of a nitride layerhaving an etch selection rate for silicon oxide. Each bitline 116 b iselectrically connected to the bit line pad 114 a through the bit linecontact 114. A third interlayer insulation layer 115 a is formed on anentire face of the semiconductor substrate containing the bit linespacer 115. The third interlayer insulation layer 115 a and the secondinterlayer insulation layer 116 a are continuously patterned to form thecapacitor storage node contact 117. The capacitor storage node contact117 may be formed of polysilicon.

The lower structure of semiconductor substrate constructed of the activeregions 104 s, 104 d, the bitline contact 114, the capacitor storagenode pad 112, the bitline pattern 116, the word line pattern 113 and thecapacitor storage node contact 117 may be formed by the straightstructure.

Referring to FIG. 9, a buffer layer 118 made of PE-TEOS (Plasma EnhancedTetra Ethyl Ortho Silicate) is formed on the semiconductor substratehaving the capacitor storage node contact 117. The buffer layer 118 canbe formed to prevent the structure below the buffer layer from beingdamaged. Subsequently, an etching stop layer 120 is formed on the bufferlayer 118. Then, a mold oxide layer 121 having a high etch selectionrate as compared with the etching stop layer is formed. The etching stoplayer 120 can be formed of silicon nitride layer if the mold oxide layer121 is made of PE-TEOS material.

That is, the mold oxide layer 121, on which a capacitor storage node ofsquare type will be formed, e.g., a single layer of PE-TEOS or amultilayer containing the PE-TEOS layer, is formed thick.

FIG. 10 illustrates a process of forming a first aperture part 122, thatis, after etching a portion of the mold oxide layer until a top surfaceof the etching stop layer is exposed, to be overlapped with an upperportion of the conductive region, by using an etch mask pattern (notshown) formed by, for example, a square type. To prevent an excessiveetching, the etching is preferably stopped at the etching stop layer120. The etch mask can be formed of polysilicon.

Referring to FIG. 11, after etching a portion of the mold oxide layer121, the etching stop layer 120 is removed, and the buffer layer 118 isetched to form the first aperture part 122 for exposing the capacitorstorage node contact 117. The conductive region 117 exposed in the firstaperture part 122 is illustrated as the capacitor storage node contact117 in the drawing. This conductive region may be in communication witha source region of the transistor.

Referring to FIG. 12, the capacitor storage node contact 117 exposed inthe first aperture part 122 is selectively etched, to form a secondaperture part 125 in which the capacitor storage node 123 of square typewill be formed. The second aperture part is formed by highly determiningan etch selection rate for the mold oxide layer 121, the etching stoplayer 120 and the bitline spacer 115 and by selectively dry etching onlythe capacitor storage node contact 117 exposed in the first aperturepart 122. The etching process to form the second aperture part can beappropriately formed to a depth of about 100 Å through about 3000 Å. Inaddition, if the capacitor storage node contact is formed ofpolysilicon, and when the capacitor storage node contact 117 is etchedto form the second aperture part 125, the polysilicon used as the etchmask when forming the first aperture part is removed together, thuseliminating the additional step of removing the etch mask whenseparating the capacitor storage node 123.

Referring to FIG. 13, a conductive layer for a formation of thecapacitor storage node of square type is deposited on the semiconductorsubstrate having the first aperture part 122 and the second aperturepart 125. The conductive layer is preferably formed of a material suchas amorphous silicon or polysilicon through a conventional techniquesuch as a CVD process. Further, a residual conductive layer on the moldoxide layer is removed by a planarization process to form the capacitorstorage node of square type. The planarization process may be a CMP(Chemical and Mechanical Polishing) process or an etch back process, orcan employ an anisotropic etching process. The capacitor storage nodes123 a to 123 e referred to in FIG. 13 are cross-sectional views from thecapacitor storage nodes 123 a to 123 e referred to FIG. 7. The capacitorstorage node 123 a to 123 e is electrically contacted with a sidewall ofthe selectively etched storage node contact 117.

The capacitor storage node 123 of square type can be widely applied to asemiconductor memory device for a DRAM cell. Further, the capacitorstorage node of square type can be formed by a box shape based on asolid stack structure, a cylinder type or a hemisphere (HSG) type, orothers.

According to this embodiment of the present invention, the followingadvantages can be provided in forming a capacitor storage node of squaretype.

First, there is no need to perform a process of forming a contactthrough a buffer layer, as in the prior art where a precisephotolithography and etching process is required in the process offorming the contact through use of the buffer layer. In addition, anetch mask and a storage node contact are formed of polysilicon, and inselectively etching the storage node contact, the etch mask is etchedtogether, and thus the step of removing the etch mask in separating thecapacitor storage node can be omitted. Therefore, the number ofprocesses can be reduced.

Second, the capacitor storage node may be formed in such a way that alower face of the storage node is contacted with an upper part of theetched conductive region, because of the recess at an edge portion ofupper portion of the interlayer insulation layer. Thus, an area of thestorage node is extended by the contacted area. As a result, capacitancecan be increased.

Third, the capacitor storage node may be formed by a square type toincrease a bottom critical dimension of the storage node, thus reducingthe leaning phenomenon.

Fourth, the capacitor storage node is formed being contacted with asidewall through an aperture part formed in a storage node contactextending the contact area connected electrically, thus increasingprocess stability.

It will be apparent to those skilled in the art that modifications andvariations can be made in the present invention without deviating fromthe spirit or scope of the invention. Thus, it is intended that thepresent invention cover any such modifications and variations of thisinvention provided they come within the scope of the appended claims andtheir equivalents. For instance, the storage node may be formed ofvariously varied type and material and the number of manufacturingprocesses may be added or reduced. Accordingly, these and other changesand modifications are seen to be within the true spirit and scope of theinvention as defined by the appended claims.

1. A semiconductor device comprising: a transistor formed on asemiconductor substrate; an interlayer insulating layer covering thetransistor, the interlayer insulating layer having a contact padelectrically connected with an active region of the transistor; and acapacitor storage node having a lower portion that is in contact withthe contact pad, wherein the contact pad has a recessed portion adjacentan edge portion of an upper portion of the interlayer insulation layer.2. The device as claimed in 1, wherein the contact pad is a capacitorstorage node contact.